Small Description about Gate Level Modeling Style in Verilog HDL.

Small Description about Gate Level Modeling Style in Verilog HDL.


Structural Modeling Style -

Structural Modeling Style shows the Graphical Representation of modules/ instances / components with their Interconnection. 
In Structural Modeling Style We defines that how our Components / Registers / Modules are Connected to each other using Nets/ Wires.

• Structural Modeling Style works on Concurrent Executions. 

Syntax -


Instance_name       Component_name     (Association List) ;

• Component_label can be any legal identifier and considered as the name of the instance.
• Instance_name must be the name of a pre-designed module.

Methods of Component Instantiations -

• Positional Mapping.
• Nominal Mapping.

Positional Mapping. -   

Example -

dff     u0    (clk  ,   reset    ,   din   ,    dout );


Sequence of Formal ports must be same with sequence of Actual Ports of component.



Nominal Mapping -

Example -

dff     u0     ( .clk (clk)   ,  
                    .reset  ( reset)    ,
                    .din (din),
                    .dout (dout) )   ;


No need to consider the sequence of Formal ports and Actual Ports.





Sample Programs-

• Design of 2 to 1 Multiplexer using Gate Level Modeling Style.
• Design of 4 Bit adder using 4 Full Adder (Structural Modeling Style) (Verilog Code).
• Design of 4 Bit Subtractor using Structural Modeling Style. (Verilog Code).
• Design of 4 Bit Adder cum Subtractor using Structural Modeling Style. (Verilog Code).
• Design of 4 Bit Adder cum Subtractor using Structural Modeling Style (Verilog Code).

Flip Flop Designs using Structural Modeling Style-

• Design of Toggle Flip Flop using  D-Flip Flop (Structural Modeling Style) (Verilog Code).
• Design of Master Slave Flip Flop using D-Flip Flop (Structural Modeling Style) (Verilog Code).
• Design of Toggle Flip Flop using J-K Flip Flop (Structural Modeling Style) (Verilog Code).

Shift Registers Design using Structural Modeling Style-

• 4 - Bit Serial In - Serial Out Design Using Structural Modeling Style. (Verilog Code).
• 4 - Bit Serial In - Parallel Out Design Using Structural Modeling Style. (Verilog Code).
• 4 - Bit Parallel In - Parallel Out Design Using Structural Modeling Style. (Verilog Code).

• 4 - Bit Stack Design using Structural Modeling Style (Verilog Code).
• 4 - Bit Queue Design using Structural Modeling Style (Verilog Code).