Conditional Operator (Data Flow Modeling Style) Verilog HDL

Conditional Operator (Ternary Operator) in Verilog HDL   (Data Flow Modeling Style) -




Syntax -


Method -1  (Condition)  -

assign     target    =     (Condition)     ?      (True)     :
                                                                    (False)  ;


Method -2   (Nets) -

assign     target    =     (Net)     ?      (Value_1)     :
                                                           (Value_0)  ;





Sample Programs-

• Design of 4 : 1 Multiplexer using Conditional Operator (Data Flow Modeling Style).
• Design of 1 : 4 Demultiplexer using Conditional Operator (Data Flow Modeling Style).
• Design of 4 : 2 Encoder using Conditional Operator (Data Flow Modeling Style).
• Design of 2 : 4 Encoder using Conditional Operator (Data flow Modeling Style).
• Design of Binary to Excess3 Code Converter using Conditional Operator (Data Flow Modeling Style).
• Design of BCD to 7 Segment Driver For Common Cathode using Conditional Operator.
• Design of BCD to 7 Segment Driver For Common Anode using Conditional Operator.
• Design of 2 Bit Comparator Using Conditional Operator.