Design of 4 to 2 Encoder using CASE Statements (Behavior Modeling Style) Verilog CODE -

Design of 4 to 2 Encoder using CASE Statements (Behavior Modeling Style) -

Output Waveform  :    4 to 2 Encoder

Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : encoder4_2
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 4 to 2 encoder using case statement.v


module encoder4_2 ( din ,dout );

output [1:0] dout ;
reg [1:0] dout ;

input [3:0] din ;
wire [3:0] din ;

always @ (din) begin
case (din)
8 : dout = 0;
4 : dout = 1;
2 : dout = 2;
1 : dout = 3;
default : dout = 1'bZ;
endcase
end

endmodule