Design of Frequency Divider (Divide by 2) using Behavior Modeling Style. (Verilog CODE).

Design of Frequency Divider (Divide by 2) using Behavior Modeling Style -

Output Waveform   :  Frequency Divider (Divide by 2).

Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : frequency_divider_by2
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of Frquency Divider (divide by 2).v


module frequency_divider_by2 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg m ;

initial m = 0;

always @ (posedge (clk)) begin
m <= ~m;
end

assign out_clk = m;


endmodule