Design of 2 to 4 Decoder using CASE Statements (Behavior Modeling Style) Verilog CODE-

Design of 2 to 4 Decoder using CASE Statement (Behavior Modeling Style) -

Ouput Waveform :  2 to 4 Deoder

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : decoder2_4
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 2 to 4 decoder using case statement.v


module decoder2_4 ( din ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input [1:0] din ;
wire [1:0] din ;


always @ (din) begin
case (din)
0 : dout = 8;
1 : dout = 4;
2 : dout = 2;
default : dout = 1;
endcase
end

endmodule