Design of 1 to 4 Demultiplexer using IF-ELSE statements (Behavior Modeling Style). (Verilog CODE).

Design of 1 to 4 Demultiplexer using if-else Statements (Behavior Modeling Style) -

Output Waveform :   1 to 4 Demultiplexer

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : demultiplexer1_4
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 1 to 4 Demultiplexer using if else statement.v



module demultiplexer1_4 ( din ,sel ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input din ;
wire din ;
input [1:0] sel ;
wire [1:0] sel ;

always @ (din or sel) begin
if (sel==0)
dout = {din,3'b000};
else if (sel==1)
dout = {1'b0,din,2'b00};
else if (sel==2)
dout = {2'b00,din,1'b0};
else
dout = {3'b000,din};
end

endmodule