Design of Integer Counter using Behavior Modeling Style (Verilog CODE)-

Design of Integer Counter using Behavior Modeling Style -

Output Waveform :   Integer Counter

Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : counter_integer
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of integer counter using Behavior Modeling Style.v


module counter_integer ( clk ,reset ,dout );

output [9:0] dout ;
reg [9:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout < 1023)
dout <= dout + 1;
else if (dout==1023)
dout <= 0;
end


endmodule