Design of 4 to 1 Multiplexer using case statements (Behavior Modeling Style) Verilog CODE -

Design of 4 to 1 Multiplexer using case statements (Behavior Modeling Style) -

Output Waveform :   4 to 1 Multiplexer

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : multiplexer4_1
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 4 to 1 multiplexer using case statement.v



module multiplexer4_1 ( din ,sel ,dout );

output dout ;
reg dout ;

input [3:0] din ;
wire [3:0] din ;
input [1:0] sel ;
wire [1:0] sel ;

always @ (din or sel) begin
case (sel)
0 : dout = din[3];
1 : dout = din[2];
2 : dout = din[1];
default : dout = din[0];
endcase
end

endmodule