Design of 8 nibble queue using Behavior Modeling Style -
Output Waveform : 8 nibble queue Design |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : queue_8nibble
// Design : verilog upload 4
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File : 8 nibble queue design using behavior modeling style.v
module queue_8nibble ( din ,clk ,push ,pull ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input push ;
wire push ;
input pull ;
wire pull ;
reg [3:0]queue[0:7];
integer i;
initial i = 0;
always @ (posedge (clk)) begin
if (push) begin
queue[i] <= din;
if (i<7)
i <= i +1;
end
else if (pull) begin
dout <= queue[0];
queue[0] <= queue[1];
queue[1] <= queue[2];
queue[2] <= queue[3];
queue[3] <= queue[4];
queue[4] <= queue[5];
queue[5] <= queue[6];
queue[6] <= queue[7];
if (i>0)
i <= i -1;
end
end
endmodule
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