Design of Parallel IN - Parallel OUT Shift Register using Behavior Modeling Style (Verilog CODE).

Design of Parallel IN - Parallel OUT Shift Register using Behavior Modeling Style -

Output Waveform :   Parallel IN - Parallel OUT  Shift Register.

Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : PIPO
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : parallel IN - Parallel OUT Shift Register using Behavior Modeling Style.v


module PIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end

endmodule