Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) Verilog CODE

Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) -

Output Waveform :   4 Bit Subtractor

Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : subtractor_4bit
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit Subtractor using loops.v


module subtractor_4bit ( a ,b ,diff ,borrow );

output [3:0] diff ;
reg [3:0] diff ;
output borrow ;
reg borrow ;

input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;

reg [4:0]s;
wire [3:0]l;

assign l = ~ b;

integer i;

always @ (a or b) begin
s[0] = 1;
for (i=0;i<=3;i=i+1) begin
diff[i] = a[i] ^ l[i] ^ s[i];
s[i+1] = (a[i] & l[i]) | (l[i] & s[i]) | (s[i] & a[i]) ;
end
borrow = s[4];
end

endmodule