Design of 4 Bit Serial IN - Parallel OUT Shift Register using D_flip flop (Structural Modeling Style) Verilog CODE.

Design of 4 Bit Serial IN   -   Parallel OUT Shift Register using  D-flip flop (Structural Modeling Style).

Output Waveform :    Serial IN   -   Parallel OUT  (Shift Register).

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : sipo
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of Serial In - Parallel Out Shift Register using d_flip flop.v


module sipo ( din ,clk ,reset ,dout );

output dout ;

input din ;
input clk ;
input reset ;  
wire [3:0]s;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));


d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));


d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));


d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(s[3]));

assign dout = s;


endmodule




// -------------- D flip flop  design - -----------------------



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : d_flip_flop.v



module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end

endmodule