Design of Frequency Divider (Divide by 8) using Behavior Modeling Style (Verilog CODE)-

Design of Frequency Divider (Divide by 8) using Behavior Modeling Style -

Output  Waveform :   Frequency Divider (Divide by 8).

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : frequency_divider_by8
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of Frequency Divider (Divide by 8).v


module frequency_divider_by8 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg [2:0]m;

initial m = 0;

always @ (posedge (clk)) begin
m <= m + 1;
end

assign out_clk = m[2];


endmodule