Design of 8 Nibble RAM (memory) using Behavior Modeling Style (VHDL Code).

Design of 8 Nibble RAM (memory) using Behavior Modeling Style -

Output Waveform :   8 nibble RAM (memory design).

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : RAM
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 8 Nibble (RAM) Memory.v


module RAM ( en ,nrw ,addr ,din ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input en ;
wire en ;
input nrw ;
wire nrw ;
input [2:0] addr ;
wire [2:0] addr ;
input [3:0] din ;
wire [3:0] din ;

reg [3:0]mem[0:7];

initial begin
 mem[0] = 15;
 mem[1] = 14;
 mem[2] = 13;
 mem[3] = 12;
 mem[4] = 11;
 mem[5] = 10;
 mem[6] = 9;
 mem[7] = 8;
end

always @ (en or nrw or addr or din) begin
if (en) begin
if (!nrw) begin
dout = mem [addr];
end
else begin
mem[addr] = din;
end
end
end

endmodule