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Design of Toggle Flip Flop using Behavior Modeling Style -
 |
| Output Waveform : Toggle Flip Flop |
Verilog CODE-
//-----------------------------------------------------------------------------
//
// Title : t_flip_flop
// Design : verilog upload 2
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File : Toggle Flip Flop using Behavior Modeling Style.v
module t_flip_flop ( t ,clk ,reset ,dout );
output dout ;
reg dout ;
input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
if (t)
dout <= ~dout;
end
end
endmodule
7 comments :
what about negative edge?
this is syncronous....
if it is asyncronous then go for
always@(posedge clock or negedge reset)
begin
if(reset)
dout <= 1'b0;
else
dout <= ~dout;
end
im getting errors in quartus tool
im getting errors in quartus tool
I think so it should be -
always@(posedge clock or negedge reset)
begin
if(!reset) //reset should be have a negation.
dout <= 1'b0;
else
dout <= ~dout;
end
I think so it should be -
always@(posedge clock or negedge reset)
begin
if(!reset) //reset should be have a negation.
dout <= 1'b0;
else
dout <= ~dout;
end
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