Design of First In - First Out (FIFO) Register using Behavior Modeling Style -

Design of First In - First Out (FIFO) Register using Behavior Modeling Style -

Output Waveform : First IN - First OUT (FIFO) Register.

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : first_in_first_out
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of First in - First out register.v


module first_in_first_out ( en ,clk ,din ,dout );

output dout ;
reg dout ;

input en ;
wire en ;
input clk ;
wire clk ;
input din ;
wire din ;

reg [3:0] mem;

initial mem = 0;

always @ (posedge (clk)) begin
if (en) begin
dout <= mem[0];
mem <= {din , mem[3:1]};
end
end

endmodule