Design of Master Slave Flip Flop using D Flip Flop (Structural Modeling Style) (Verilog CODE).

Design of Master Slave Flip Flop using D Flip Flop (Structural Modeling Style) -

Output Waveform :   Master Slave Flip Flop

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : master slave flip flop using D flip flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of master slave flip flop using d_flip flop.v


module master_slave_ff ( din ,clk ,reset ,dout );

output dout ;

input din ;
input clk ;
input reset ;  

wire s;
wire in_clk;

assign in_clk = ~clk ;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s));

d_flip_flop u1 (.din(s),
.clk(in_clk),
.reset(reset),
.dout(dout));

endmodule




// -------------- D flip flop  design - -----------------------



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : d_flip_flop.v



module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end

endmodule