Logical Operators test in Verilog HDL Design

Basic Logical Gates Design using Data Flow Modeling Style-

Output Waveform  :   Logical Gates in Verilog HDL

Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : Gate_Test
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Gate Test.v


module Gate_Test ( a ,b ,c ,d ,e ,f ,g ,h ,i ,j );

output c ;
output d ;
output e ;
output f ;
output g ;
output h ;
output i ;
output j ;

input a ;
input b ;

assign c = a & b;
assign d = a | b;
assign e = ~a;
assign f = ~b;
assign g = ~(a & b);
assign h = ~(a | b);
assign i = a ^ b;
assign j = a ^~ b;

endmodule