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4 : 2 Decoder Design using Logical Gates (Data Flow Modeling Style)-
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : encoder4_2
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 4 to 2 Encoder Design using Logical Gates.v
module encoder4_2 ( a ,b ,c ,d ,x ,y );
output x ;
output y ;
input a ;
input b ;
input c ;
input d ;
assign x = b | d;
assign y = c | d;
endmodule
 |
| Output Waveform : 4 : 2 Decoder |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : encoder4_2
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 4 to 2 Encoder Design using Logical Gates.v
module encoder4_2 ( a ,b ,c ,d ,x ,y );
output x ;
output y ;
input a ;
input b ;
input c ;
input d ;
assign x = b | d;
assign y = c | d;
endmodule
10 comments :
why is the input 'a' never used?
why is the input 'a' never used?
why is the input 'a' never used?
thank you sir for your wonderful work
thank you
thank you
Send Bob and vagene
Sir thanks
Sir nanum Naresh dha sir
Q. why is the input 'a' never used?
A. Use K-map for 4 to 2 encoder, you will get x=b+d , y=c+d.
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