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Design of 4 Bit Binary Counter using Behavior Modeling Style -
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| Output Waveform : 4 Bit Binary Counter |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : Counter_4Bit
// Design : verilog upload 4
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File : Design of 4 Bit Counter using Behavior Modeling Style.v
module Counter_4Bit ( clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
8 comments :
Will you please provide the explanation also...?
Will you please provide the explanation also...?
will u please provide the test bench for it?
module Counter_4BitTestBench;
reg clk;
reg reset;
wire [3:0] dout ;
parameter step = 100;
Counter_4Bit uut (clk, dout , reset);
always begin
clk = 0; #(step/2);
clk = 1; #(step/2);
end
initial begin
reset = 0;
#step reset = 1;
#(step*20) $finish;
end
initial $monitor($stime," clk = %b, reset = %b, dout = %h",clk,reset,dout );
endmodule
Need verilog code for a counter which counts the given sequence
First the inputs clock, reset are declared as"inputs", since it's for 4bit counter so the output is [3:0] it's a code for synchronus counter where for every positive cycle the counter starts counting.
First we need to initialise the counter as 0
Then after every positive cycle the counter will start counting
Is it synchronous or asynchronous counter?
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